| # | Track | Paper Title | Author 1 |
|---|---|---|---|
| 1 | AI-Powered Digital Design and Implementation | Power Improvement Strategies Using Genus and Innovus RTL2GDS Solution | Prateek Omer, Google Sachin Waghmare, Google |
| 2 | Digital Front-End Design, Test and Implementation | Automated Optimized ECO Patch Generation Using Conformal ECO Recipes | Sneha Biswas, Intel Suprita Kulkarni, Cadence |
| 3 | Digital Signoff | ECO Strategy for BIG DIE SOC Convergence | Sabya Sachi Sahu, Samsung Aniket Agrawal, Samsung Pushpendra Singh Yadav, Samsung |
| 4 | Custom and Analog Design - Implementation | Accelerate, Adapt, Advance: Efficient Migration Strategies for High-Speed Layouts | Spoorthi S, Samsung Wasimahmed Bepari, Samsung |
| 5 | Custom and Analog Design - Verification | Innovative and Impactful Way of Power Leakage Analysis in Full-Chip AMS Simulation | Pavan Vernekar, Infineon Murali Gopala Krishna, Infineon Pradeep Kumar Marikundam, Infineon Chaithra KP, Infineon |
| 6 | Advanced Verification Methodology | Midas USF Framework to Enable FMEDA Automation for Accelerated Functional Safety Certification | Subham Mohapatra, Texas Instruments Pratibha Gupta, Texas Instruments Yogeshwaran Shanmugam, Texas Instruments Tanmoy Sarkar, Texas Instruments |
| 7 | Hardware and System Verification | Accelerating Pre-Silicon GPU Benchmark Performance Verification Using Cadence Performance Verification Solution on Palladium | Srinivasulu Reddy Alamuri, Samsung Sooraj S, Samsung Harsh Setia, Samsung Drippin Reagan Sargunaraj, Samsung |
| 8 | IP Characterization | Improving Design Robustness with Advanced Aging Solution | Ajoy Mandal, Texas Instruments Muthu A L, Texas Instruments Megha Sharma, Texas Instruments Chirayu Amin, Cadence Vandit Koshta, Cadence Himanshu Tanwar, Cadence |
| 9 | PCB and System Design and Analysis | PCIe Gen6 Simulation Challenges Faced and Solved Using Sigrity X | Siva Kumar NM, L&T Technology Services Kumaran M, L&T Technology Services Vijaya Varma K, L&T Technology Services Poosanalakshmi G, L&T Technology Services Nikitha P, L&T Technology Services |
| 10 | Performance and Smart Bug Hunting | Accelerating RTL Design Verification: A Unified Static and Dynamic Approach for RTL Design Glitch Detection and Timing Constraint Exceptions (SDC) Verification | Madhav Boddhapu, Google Pandithurai Sangaiyah, Google Karishma Singh, Cadence |