CadenceLIVE India 2025

Agenda Page

August 13, 2025 Sheraton Grand Bengaluru

AGENDA

August 13, 2025

AGENDA

TRACK 1 - AI-POWERED DIGITAL DESIGN AND IMPLEMENTATION

13-08-2025 09:30 am

Power Improvement Strategies Using Genus and Innovus RTL2GDS Solution - Google

Scarlet Ballroom 1

Prateek Omer
Google India

13-08-2025 10:00 am

Achieving Best-in-Class PPA Using Cadence Cerebrus Apps - Broadcomm

Scarlet Ballroom 1

Prashant Kumar Vallbhabhai Bhut
Broadcom

Ali Ahmed
vfairs

13-08-2025 10:30 am

Pushing Boundaries in Innovus for a Complex High-Speed, High-Macro-Count Third-Party Multimedia Subsystem IP - MediaTek

Scarlet Ballroom 1

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - AI-Powered Digital Design and Signoff

Convention Hall

13-08-2025 02:15 pm

Scalable Methodology for Area-Efficient and Power-Optimized ARM CPU Core Design in Advanced Node Using Cadence Cerebrus and PSDL - Samsung

Scarlet Ballroom 1

13-08-2025 02:45 pm

Maximizing Dynamic Power Reduction on a 5nm Design Using Cadence Cerebrus - Analog Devices

Scarlet Ballroom 1

Shvetha Natarajan
Analog Devices

13-08-2025 03:30 pm

Implementation of High-Speed Peripheral Component Interconnect Express (Gen-5), Ensuring Good PPA and Smooth Closure With Genus i-Spatial - Qualcomm

Scarlet Ballroom 1

Rajeev Mishra
Qualcomm

Talawara Manjunath
Qualcomm

sonu Nehra
Qualcomm

Subhashini Singh
Qualcomm

Nitin Kaushik
qualcomm

13-08-2025 04:00 pm

AI-Powered Automations: Unlocking PPA Gains with Cadence Cerebrus and Cadence JedAI - Samsung

Scarlet Ballroom 1

Shammi Kumar
Qualcomm Technologies, Inc

13-08-2025 04:30 pm

Shift-Left Heuristic-Driven Automated Dynamic Scaling Model for Faster Timing Convergence and Power Reduction - Rambus

Scarlet Ballroom 1

Amogh KM
Rambus

Lakshman Kalpathy Venkiteswaran
Rambus

Dinesh Kumar Gangatharan
Rambus

Sai Sumukha K V
Rambus

13-08-2025 05:00 pm

Enhancing PPA of Digital Designs Using Various APPs in Cadence Cerebrus – ML Engine - Texas Instruments

Scarlet Ballroom 1

Bala Subrahmanyam
Texas Instruments

13-08-2025 05:30 pm

AI/ML-Driven Mixed Placer Flow for Better Turnaround Time and PPA - Intel

Scarlet Ballroom 1

SAI KRISHNA KAIRAMKONDA
intel

TRACK 2 - DIGITAL FRONT-END DESIGN AND TEST

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - AI-Powered Digital Design and Signoff

Convention Hall

13-08-2025 02:15 pm

Unlocking Deeper Insights in RTL Development Using Joules RTL Design Studio - Texas Instruments

Convention Hall

Eswar Pentakota
Texas Instruments

13-08-2025 02:45 pm

Advanced Activity-Aware Gating Methodologies for Power Reduction in High-Frequency Multi-million Core Design Using the Latest Technology Node - Intel

Convention Hall

Sanjit Sharma
RIVOS INC

13-08-2025 03:30 pm

End2End CECO Flow for Rapid ECO Convergence - AMD

Convention Hall

Chaitanyh Singh
Advanced Micro Devices

Akhilesh Reddy Gillela
AMD India Pvt Ltd

Anandhan M
AMD

13-08-2025 04:00 pm

ML Method to Optimize Test Point Insertion in an SoC - Texas Instruments

Convention Hall

Sujeet Maurya
Texas Instruments India Pvt. Ltd.

Vishal Diwan
Texas Instruments

13-08-2025 04:30 pm

Automated Optimized ECO Patch Generation Using Conformal ECO Recipes - Intel

Convention Hall

Sneha Biswas
Intel

13-08-2025 05:00 pm

Best DFT Design Practices for Smooth Timing Convergence of Odd Floorplan with Hard Macros Covering Large Floor Plan Distances - Qualcomm

Convention Hall

Ali Ahmed
vfairs

13-08-2025 05:30 pm

Hybrid TPI: A Unified Test Point Insertion Strategy for Improved Coverage with Design Optimization - Microchip

Convention Hall

Yadukrishnan Gopinathan
Microchip Technology India PVT LTD

TRACK 3 - DIGITAL SIGNOFF

13-08-2025 09:30 am

Automated In-Design Prevention and Fixation Through Shift Left Methodology in Existing CAD Flows - Microsoft

Amaryllis

13-08-2025 10:00 am

Refining PDN Signoff with Voltus - Qualcomm

Amaryllis

Kumar Shubham
qualcomm

Prathamesh Pathak
Qualcomm

13-08-2025 10:30 am

XM Flow for Closure of Power Integrity of Very Large Designs - RIVOS

Amaryllis

Sanjit Sharma
RIVOS INC

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - AI-Powered Digital Design and Signoff

Convention Hall

13-08-2025 02:15 pm

Voltus Insight AI-Based In-Design EM-IR Fixing - Google

Amaryllis

13-08-2025 02:30 pm

Accelerating Power Integrity Signoff using Cadence Voltus in FinFET Designs: Optimization for IR Drop and EM Analysis - Samsung

Amaryllis

13-08-2025 02:45 pm

ECO Strategy for BIG DIE SOC Convergence - Samsung

Amaryllis

13-08-2025 04:00 pm

Tempus STA Signoff in PPA Critical Cores - Qualcomm

Amaryllis

Ankit Gupta
Qualcomm

13-08-2025 04:30 pm

Accelerated Design Closure Using High-Capacity ECO and Custom Automation for Timing Signoff - Texas Instruments

Amaryllis

Vidushi Gaur
Texas Instruments

13-08-2025 05:30 pm

Cascaded Clock Mesh Analysis for Big Die SOC - Samsung

Amaryllis

TRACK 4 - CUSTOM AND ANALOG DESIGN: IMPLEMENTATION

13-08-2025 09:30 am

A Novel Methodology for Qualification of Voltage Dependent Rule Flows - Intel

Poinsettia

PRIYANKA SHARMA
Intel Technology India Pvt. Ltd.

Rahul Hebbar P R
INTEL

13-08-2025 10:00 am

Digital Implementation in Automotive Analog IPs Using APR Virtuoso-MXL in 18nm Technology - STMicroelectronics

Poinsettia

13-08-2025 10:30 am

Matched Placement and Routing Using Virtuoso Studio Group Array - NXP

Poinsettia

Akshita Bansal
Cadence Design Systems

Akshita Bansal
Cadence Design Systems

Priyanka Madaan
NXP India Pvt. Ltd.

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - Custom and Analog Design: Implementation

Poinsettia

13-08-2025 02:15 pm

Application Readiness Checker (ARC): Binding Using LVS Results Database - STMicroelectronics

Poinsettia

Shikha Prajapati
STMicroelectronics

13-08-2025 03:30 pm

Design Review Assistant: Empowering Layout Reviewers With Intelligent Feedback Tool - NXP

Poinsettia

Akshita Bansal
Cadence Design Systems

13-08-2025 04:00 pm

Breaking the Productivity Barrier in Analog Layout Design: A Paradigm Shift Using APR Flow - Western Digital & SanDisk

Poinsettia

13-08-2025 04:30 pm

Node-to-Node Layout Migration Simplified with Virtuoso Studio - Intel

Poinsettia

13-08-2025 05:00 pm

Accelerate, Adapt, Advance: Efficient Migration Strategies for High-Speed Layouts - Samsung

Poinsettia

SPOORTHI S S
Samsung Semiconductors

13-08-2025 05:30 pm

Layout Productivity Improvement Using Virtuoso Studio Advanced Routing Features - Qualcomm

Poinsettia

Satish Kumar Beja
Qualcomm

Neha Raskar
QUALCOMM INDIA

Kanika Gupta
NXP Semiconductors

TRACK 5 - CUSTOM AND ANALOG DESIGN: VERIFICATION

13-08-2025 09:30 am

Fast and Accurate Simulation of RADAR SOCs With Spectre FX FastSPICE Simulator - NXP

Petunia

SAINATH KARLAPALEM
NxP

Atishkumar Savale
NXP Semiconductors

13-08-2025 10:00 am

Overcoming ICFB’s CPU Limitation in Maestro - Texas Instruments

Petunia

Sarah Smith
TEXAS INSTRUMENTS

ashf ali
vfa

13-08-2025 10:30 am

Testbench Framework for Mixed-Signal Verification of SOC With UPF-Enabled Design - STMicroelectronics

Petunia

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - Custom and Analog Design: Verification

Petunia

13-08-2025 02:15 pm

[SMS] Schematic Migration Sprint©: Revolutionizing Cross-Technology Schematic Migration - Intel

Petunia

Dr Javed GS
Intel Foundry

Shubham Sachdeva
Intel

Sukanta Saha
Intel

Anshaj Shrivastava
Intel

13-08-2025 02:45 pm

Automation of Analog Module Using Virtuoso Schematic Parameterized Cells and Modgen for Efficient IP Development - NXP

Petunia

Kanika Gupta
NXP Semiconductors

13-08-2025 03:30 pm

Optimizing Sigma Delta ADC Design With AI-ML-Enabled Spectre-FMC Solution - STMicroelectronics

Petunia

Vaibhav Garg
STMicroelectronics

13-08-2025 04:00 pm

Impactful Way of Power Leakage Analysis in Full-Chip AMS Simulation [Combination of “Cadence Spectre-fx Fast-Spice Simulator + Artificial Intelligence (AI)”] - Infineon

Petunia

13-08-2025 04:30 pm

Spectre Transient Electrothermal Analysis Using Celsius as a Co-Simulator - Texas Instruments

Petunia

13-08-2025 05:00 pm

Enabling Static Timing Analysis and Digital Verification on High-Speed Custom AMS Design Using Cadence Virtuoso Studio - Micron

Petunia

Ravi Shekhda
Micron Technology

Sunny Sharma
Micron Technology Operations India LLP

Ronak Pandya
Micron Technology Operations India LLP

NARENDRA MANCHINEELLA
Micron Technology Operations India LLP

13-08-2025 05:30 pm

Dynamic ESD Analysis Using Voltus XFI ESD - Intel

Petunia

TRACK 6 - ADVANCED VERIFICATION METHODOLOGY

13-08-2025 09:30 am

Timing Constraint Verification of a Modem SoC - Samsung

Scarlet Ballroom 2

13-08-2025 10:00 am

High Performance Computing Multi-Die Simulation: A Parallel Computing Approach for Next-Generation System Design Verification

Scarlet Ballroom 2

13-08-2025 10:30 am

Triple Check: The Key to Shift-Left PCIe Verification Closure with Testbench Automation and Direct Leverage of Comprehensive Test-Suites - Samsung

Scarlet Ballroom 2

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - System Design and Verification

Scarlet Ballroom 2

13-08-2025 02:15 pm

Midas USF Framework to Enable FMEDA Automation for Accelerated Functional Safety Certification - Texas Instruments

Scarlet Ballroom 2

Subham Mohapatra
Texas Instruments

13-08-2025 02:45 pm

Revolutionizing Verification with AI: Enhancing Efficiency, Reducing Risks, and Improving Quality - Samsung

Scarlet Ballroom 2

Aishwarya Patil
Samsung Semiconductor India Research

Sushree Bandita Panda
SSIR

13-08-2025 03:30 pm

Bridging the Complexity Gap: Formal Verification for SOC Power Management State Machines (Executable Spec to Coverage Closure) - Samsung

Scarlet Ballroom 2

13-08-2025 04:00 pm

From Chaos to Clarity: Unraveling Unclassified Faults with Concurrent Simulator - Analog Devices

Scarlet Ballroom 2

Siri Rajanedi
Analog Devices India pvt ltd

13-08-2025 04:30 pm

Novel Approach For Verification of Homogeneous Multi-Die Booting Using Cadence NDIE Methodology - Samsung

Scarlet Ballroom 2

Manikanta Gummadidala
Samsung Semiconductor India Research Bangalore

13-08-2025 05:00 pm

Advanced Low-Power Verification Framework Integrating Formal and Dynamic Simulations for Complex Processor SOCs - Texas Instruments

Scarlet Ballroom 2

Ayushi Bapna
Texas Instruments

13-08-2025 05:30 pm

GLS Shift Over Through Timing Constraint Verification - Samsung

Scarlet Ballroom 2

Amey Telang
Samsung Semiconductor India

Amey Telang
Samsung Semiconductor India

TRACK 7 - PERFORMANCE AND SMART BUG HUNTING

13-08-2025 09:30 am

Holistic Verification Closure for AI Accelerator Device Using CDNS PCIe Gen6 VIP - Meta

Heliconia

Meghvendra Sinh Rathod
Meta Platforms Inc

13-08-2025 10:00 am

Ensuring Cryptographic Integrity: Formal Verification for Security IPs - STMicroelectronics

Heliconia

Sarvesh Tiwari
STMicroelectronics

13-08-2025 10:30 am

Evolving from debugging to AI-Enhanced Solutions using Verisium AI

Heliconia

Pamarthy Gopika Rani Alekhya
Analog Devices

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 02:15 pm

Accelerating RTL Design Verification: A Unified Static and Dynamic Approach for RTL Design Glitch Detection and Timing Constraint Exceptions (SDC) Verification - Google

Heliconia

Madhav Boddhapu
Google

13-08-2025 02:45 pm

Adaptive Randomization Exploration Solver (ARES), A Part of Verisium SimAI for Analyzing and Automatically Improving Randomizations in Regression Testing - Qualcomm

Heliconia

13-08-2025 03:15 pm

Overcoming Verification Challenges in PCIe IDE Controllers for Automotive Applications - MediaTek

Heliconia

13-08-2025 04:00 pm

Accelerating Design Verification: A Case Study of AI/ML-Driven Debug and Smart Regression Management Using Verisium Apps - Texas Instruments

Heliconia

Jaswanth Kumar Reddy Ambhati
Texas Instruments

13-08-2025 04:30 pm

Novel Formal Equivalence Approach to Verify Yield Improvement in Complex Design - Qualcomm

Heliconia

Sanjana Jain
Qualcomm

13-08-2025 05:00 pm

Accelerating Design Verification Process with Cadence Xcelium SIMAI - Samsung

Heliconia

Abhishek Kulkarni
Samsung Semiconductor India Research

Abhishek Bidhan
Samsung Semiconductor India Research

Himanshu Chauhan
Samsung India

13-08-2025 05:30 pm

Optimize Regression and Maximize Coverage by 10X Using SimAI - NVIDIA

Heliconia

Ali Ahmed
vfairs

Ali Ahmed
vfairs

TRACK 8 - HARDWARE AND SYSTEM VERIFICATION

13-08-2025 09:30 am

LPDDR Theoretical Bandwidth Estimation Through AC Timing Analysis - Google

Hibiscus

Anirban Majumder
Google IT Services India Pvt Ltd

13-08-2025 10:00 am

Accelerating GPU Benchmark Performance Verification Using a Palladium APV Methodology - Samsung

Hibiscus

sooraj s
Samsung Semiconductor India Research

sreenivasulu Reddy Alamuri
SAMSUNG SEMICONDUCTOR INDIA RESEARCH

13-08-2025 10:30 am

Skillful Exploration and Performance Evaluations Using Emulation Hardware Palladium for ARM-Based MCUs: Use Cases on Dhrystone and CoreMark - STMicroelectronics

Hibiscus

ASHUTOSH BISHT
STMicroelectronics

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 02:00 pm

MTIA Hybrid Emulation for System Validation of Multi-Chiplet ML SoC’s

13-08-2025 02:15 pm

Accelerating Multimedia Scenario Verification and SW Validation Shift Left Using UVMA on PZ2 - Samsung

Hibiscus

13-08-2025 02:45 pm

Enhanced Regression Planning and Failure Analysis Using vManager APIs for Windows-Based Regressions - Texas Instruments

Hibiscus

Pranali Gaydhane
Texas Instruments

13-08-2025 03:30 pm

Silicon Bug Reproduction with Perspec Coherency Solution - Google

Hibiscus

Nidhi Makwana
Google

Ravi Mangal
Google India

Preethi Ashok Kumar
Google

13-08-2025 04:00 pm

Layered Integration of Portable Stimulus Environment with Legacy SOC Testbench: Harnessing PSS Power to Retarget DV Test Intent Across Heterogeneous Execution Platforms - Samsung

Hibiscus

13-08-2025 04:30 pm

Secure and Scalable Emulation Compile Flow on Google Cloud Platform (GCP) - Google

Hibiscus

Alok Mistry
Google

Aditya Chitrode
Google India

13-08-2025 05:00 pm

DFT-Accelerated Serial DFT SOC Scan Validation Using PALLADIUM Emulator - Samsung

Hibiscus

13-08-2025 05:30 pm

Leveraging Palladium for Accurate Dynamic Power Profiling in Low-Power SoCs - Analog Devices

Hibiscus

Vivek Gopalkrishna
Analog Devices Inc

TRACK 9 - PCB AND SYSTEM DESIGN AND ANALYSIS

13-08-2025 09:30 am

Leveraging Allegro X Advanced Package Designer Platform to Build Efficient Multi-Chiplet Heterogeneous Package for AI Application - Ola Kutrim

Scarlet Ballroom 3

Sheetal Jain
Krutrim SI Designs

13-08-2025 10:00 am

Distributed Ground Extraction for Packages - SanDisk

Scarlet Ballroom 3

ABHISHEKH M L
Sandisk Technologies, Inc.

Vijay Kumar Singh
Sandisk Technologies, Inc.

TAMILHARASAN M
Sandisk Technologies, Inc.

13-08-2025 10:30 am

PCIe Gen6 Simulation Challenges Faced and Solved Using Sigrity X - L&T Technology Services

Scarlet Ballroom 3

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 01:30 pm

Cadence Technology Update - PCB and System Design and Analysis

Scarlet Ballroom 3

13-08-2025 02:15 pm

Simulate with Confidence: The Ultimate Solution for High-Frequency RF PCB EM Analysis in MWO Cross-Platform Flows/Solutions - Craftronics

Scarlet Ballroom 3

Gayetri Gayetri
Craftronics India Pvt Ltd

13-08-2025 02:45 pm

Enhancing Complex Server Design with Allegro System Capture - Lenovo

Scarlet Ballroom 3

Saurav Kumar
Lenovo

Shyju K M
Lenovo

13-08-2025 02:45 pm

Time Efficient Flow to Achieve Spec-Compliant RFIC Passive Designs - Qualcomm

Scarlet Ballroom 3

13-08-2025 03:30 pm

Analysing DDR5 CA bus Using Clarity TDR Tool - Micron

Scarlet Ballroom 3

Upender Dharavath
Micron Technology Operations India LLP

13-08-2025 04:00 pm

Cadence Optimality - Infineon

Scarlet Ballroom 3

13-08-2025 04:30 pm

SI/PI Analysis for Layout Engineers Using Sigrity Aurora PCB - Intel

Scarlet Ballroom 3

13-08-2025 05:00 pm

Thermomechanical Warpage Analysis of a BGA Package During Reflow Soldering Using Cadence Celsius Studio - MaxLinear

Scarlet Ballroom 3

Jayanth Venkatesh
MaxLinear Inc

13-08-2025 05:00 pm

IP validation using Liberate_LV and Liberate Insigh

Santhosh Kamatam
NXP semiconductor

13-08-2025 05:30 pm

Cadence X AI-Driven PCB Design Optimization - Qualcomm

Scarlet Ballroom 3

TRACK 10 - IP CHARACTERIZATION

13-08-2025 10:00 am

Distributed Ground Extraction for Packages

13-08-2025 10:55 am

Tea Break

13-08-2025 11:30 am

Cadence Keynote

Convention Hall

13-08-2025 12:00 pm

Guest Keynote

Convention Hall

13-08-2025 12:30 pm

Lunch Break

13-08-2025 02:15 pm

Standard Cell Level Benchmarking Using Cadence Liberate Insight

Zinnia

13-08-2025 02:45 pm

Full Chip STA in Lattice Semiconductor Using Liberate AMS - Lattice Semiconductor

Zinnia

13-08-2025 03:30 pm

Optimized Library Benchmarking Using Liberate Trio MPVT Flow and LDBX - Analog Devices

Zinnia

Mallikarjun Baragali
Analog Devices

13-08-2025 04:00 pm

Improving Design Robustness with Advanced Aging Solution

Zinnia

Himanshu Tanwar
Cadence Design Systems

13-08-2025 04:30 pm

Accurate Library Characterization and Validation Checks with Liberate-TRIO for Better PPA - Samsung

Zinnia