As a Silicon Engineer at Google India, Prateek Omer brings deep expertise in GPU implementation. His work centers on optimizing hardware for high-performance computing, with a key focus on analyzing and optimizing designs for power efficiency, thereby enhancing the overall PPA of GPU designs.

Sachin Waghmare is a seasoned Physical Design Engineer with over a decade of experience specializing in the semiconductor industry. He holds a Master's degree in Electrical Engineering from IIT Madras, where he honed his expertise in VLSI design. For the past 11 years, Sachin has been at the forefront of implementing advanced Physical Design strategies, consistently pushing the boundaries of performance, power, and area (PPA) optimization. His work focuses on tackling complex convergence issues and ensuring the successful tape-out of high-performance integrated circuits. Known for his meticulous approach and deep technical knowledge, Sachin is a key contributor to design teams, driving innovation and efficiency in the physical design flow, currently working for Google India.

Physical Design engineer with 13 years of experience

Amrut is a Staff Engineer specializing in Physical Design at MediaTek, where he is a member of the Multimedia team. With over 6 years of experience, he leverages his expertise to drive innovative solutions in semiconductor design implementation. Amrut has considerable experience in RTL to GDSII (R2G) processes and excels in both implementation and optimization of design and automation workflows, ensuring efficient project execution.

Kishore is working as a Staff Physical Design Engineer at MediaTek with over 8 years of hands-on experience in the semiconductor industry. His expertise spans the full spectrum of physical design, from floorplanning and placement to timing closure and signoff. He is proficient with a wide range of EDA tools and has successfully managed and delivered multiple complex SoC designs. Kishore is passionate about leveraging technology to solve challenging problems and committed to driving innovation and efficiency in every project he undertakes.

Rahul Singh, Staff Engineer specializing in Physical Design at Samsung Semiconductors India Research. 

With 8 years of dedicated experience in the semiconductor industry, Rahul has expertise in optimizing complex SoC designs and ensuring robust performance for mobile processors and automotive SoCs. 

His career spans significant roles at Wipro Limited and Waferspace , working for a diverse portfolio of tier-one clients including Intel, Qualcomm, Google, and Texas Instruments.

Anil is a Physical design engineer at Samsung Semiconductor India, specializing in advanced design optimization techniques using Cadence, synopsys tools, and Tcl scripting. He leverages innovative methodologies, thereby enhancing chip performance and efficiency for next generation semiconductor technologies.

Shvetha Natarajan is a Staff Design Engineer working on digital design implementation at Analog Devices. She received her MS in EE from North Carolina State University and BE in ECE from R.V.College of Engineering. Previously, she has worked in the Digital Implementation Flows and Methodologies teams at ADI and Synopsys.

Rajeev has over 13 years of experience, Mostly into SoC Implementation and integration domain. He obtained his Mtech Degree in Communication systems from IIT BHU in 2012. Currently he is leading SoC Implementation team in Qulacomm Noida and involved into multiple Tapeouts for different range of products. Prior to Qualcomm he has been associated with various companies like STMicro, Microsemi, Cadence.

ASIC flows automation and synthesis methodology expert at Qualcomm

Senior Engineer at Qualcomm, contributing to advanced System on Chip (SoC) design and development within the SoC Design Team.

Almost 2 Decade of semiconductor industry Experience with SOC chips catering to Auto/Mobile/Compute

I am Shammi Kumar I hold a degree in Electronics and Communication Engineering (ECE) and currently work in the implementation team, specializing in Synthesis (Synth), Logic Equivalence Checking (LEC), and Static Timing Analysis (STA). With a strong foundation in digital design and timing closure, I contribute to delivering high-quality, timing-optimized designs in the semiconductor domain. My role involves close collaboration with cross-functional teams to ensure design integrity and performance throughout the implementation flow.

Deep Kalola, an Associate Director with 12 years of industry experience, is currently contributing his expertise at Samsung. His work focuses on cutting-edge semiconductor advancements that power next-generation devices. Over the years, he has developed proficiency in various stages of the design cycle, including sign-off, managing timing complexities, and achieving physical verification closure. Additionally, he has cultivated a strong understanding of low-power checks, deployments, and pre-closure strategies to effectively address and resolve critical design issues. Outside of work, Deep enjoys playing badminton, reading novels, and exploring nature through hiking trails.

Amogh K M is a Physical Design Engineer with two years of experience in the semiconductor industry. Graduated with a B.Tech in Electronics and Communication Engineering from PES University in 2023. Work focuses on synthesis, place and route (PnR), physical verification (PV), static timing analysis (STA), and signoff.

Physical Design Engineer with 7+ years of Experience. Holds Masters in VLSI Design from Anna University, Chennai and have bachelor's from Cochin University of Science & Technology

Physical Design Engineer with 3 years of experience and skilled in synthesis, PnR, PV and STA. Alumni of RV College of Engineering. Passionate about innovating and optimizing digital systems.

I'm a Physical Design Engineer at Rambus Chip Technologies with 1.5 years of experience. I graduated from PES University in 2023. I interned at Rambus for 7 months before getting converted to a full time employee. My areas of interest include VLSI, Digital Design, Analog Circuits.

I am Bala Subrahmanyam, and I work as a Digital Design Engineer at Texas Instruments with 2 years of working experience.

I am a Sr. CAD Physical Design Engineer with over 9+ years of full-time experience in the semiconductor industry, specializing in advanced VLSI design and implementation. I hold an M.Tech from BITS Pilani and am currently pursuing a Ph.D. in VLSI Design and Automation at BITS Pilani, where my research focuses on innovative methodologies and automation in physical design. Throughout my career, I have worked extensively on: Complete RTL to GDSII flow Floorplanning, placement, clock tree synthesis (CTS), routing, and signoff Low-power design strategies and physical verification Industry-standard EDA tools including Cadence, Synopsys, and Mentor Graphics My journey reflects a strong commitment to both academic excellence and practical innovation, aiming to bridge the gap between research and real-world chip design challenges.

I'm a Digital Design Engineer at Texas Instruments with a background in embedded systems and VLSI. After graduating in 2020, I worked at Hyundai, then completed my MTech from NIT Calicut. I enjoy working on semiconductor innovations. Outside work, I love watching movies and exploring new places.

Abhishek Chouksey is currently working as a Tech lead at Intel. He holds Dual Degree with specialization in Microelectronics from IIT Bombay

AMD empowers innovation with advanced silicon engineering, where my contributions focus on RTL design, synthesis, and STA for cutting-edge technologies. I have collaborated on optimizing designs for advanced process nodes like 3nm,4nm and 5nm, enabling high-performance solutions for modern applications. A strong academic foundation from NIT Patna in Electrical, Electronics, and Communications Engineering underpins expertise in silicon design. Proficient in RTL-to-GDS flow and skilled in tools like C++ and Python, with certifications in synthesis and timing analysis to support complex SoC development.

This is Akhilesh from AMD India Pvt Ltd. Designation - MTS Design Engineer. Working in (FE-INT) Synthesis and LEC team.

https://www.linkedin.com/in/anandhan-m-025993a/

Sujeet Maurya is a DFT (Design for Test) Engineer at Texas Instruments, with over 2.5 years of experience in the field. During his tenure, he has made contributions primarily to scan insertion, ATPG (Automatic Test Pattern Generation), and GLS (Gate Level Simulation) for multiple complex System on Chips (SOCs). Sujeet holds a Master’s degree in VLSI Design from Indian Institute of Science (IISc) Bangalore. His professional interests are focused on the intersection of machine learning and SOC design, particularly in exploring innovative applications for improving test efficiency and reducing test costs. Sujeet is also passionate about system design, striving to optimize both performance and reliability in SOC testing.

Vishal Diwan is Digital Design manager leading the central DFT team for ASM-Auto Business unit in TI. He is part of Member group technical staff in Texas Instruments. He has 12 years of DFT experience and expertise across DFT flows and methodologies. He has one US patent and multiple publications in internal and external conferences. He has masters in electrical engineering from IIT Bombay in year 2013.

I am Sneha, an enthusiastic hardware engineer at Intel based in Bengaluru. I have a strong passion for learning and tackling new challenges in the VLSI Design domain. I completed my M.Tech in VLSI Design from Vellore Institute of Technology, Vellore, and my B.Tech from Netaji Subhash Engineering College, Kolkata in ECE. Beyond my professional pursuits, I find joy in singing, dancing, and constantly expanding my skillset and knowledge base. My strong dedication and inquisitive nature contribute significantly to my effectiveness in the dynamic field of semiconductor technology.

ASIC flows automation and synthesis methodology expert at Qualcomm

Yadukrishnan Gopinathan is a Digital VLSI specialist holding a Master’s degree in Digital VLSI Design from Amrita Vishwa Vidyapeetham, earned in July 2022. With 4 years of industry experience, including 3 years dedicated to the Design For Testability (DFT) domain, Yadukrishnan possesses expertise in Digital ICs, System Design, and Signal Processing. His skillset includes Scan Insertion, ATPG, Simulation, and Advanced fault modeling. He previously worked as a Silicon Design Engineer at Advanced Micro Devices (AMD) for 2.5 years and currently works as a Design Engineer specialized in Design for Testability at Microchip Technology Inc.

Adennagari Subramanyam currently working as Senior Enigineer-1 at Microchip Technology India Pvt, Ltd Bangalore with 4 years of Experience in DFT. His expertise include Advanced Fault Modelling, ATPG and Simulations. He is also involved in the Cell-Aware and Timing Aware ATPG implementations.

19+ years in physical design, developing various IP's from SerDes to Memories. Currently leading PD team of Cadence for HBM development. Have half a dozen granted US patents and several papers/posters in various conferences like CDNLive & DAC.

Kiran is working as Principal Design Engineer at Cadence. Passionate Physical Design Engineer with a strong background in ASIC implementation and a keen interest in developing innovative solutions for complex design challenges.

Working as Senior Principal Design Engineer in Cadence Design Systems

BTech from NIT, Uttarakhand, MTech from MNNIT, Allahabad Working in Qualcomm as Senior PDN Methodology Engineer

PDN/EM-IR CAD Engineer @ Qualcomm | BTech EEE @ IIT Guwahati

Over 13 years experience in the SoC PDN domain, currently leading PDN methodology team in Qualcomm

I have over 14yrs of experience working in the backend design of ASIC chips. I have worked with Qualcomm, ARM , INTEL and Synopsys in my past.

I am Praphulla Pandey, a Electrical Signoff Engineer at Google (P&D). I specialize in EMIR and power integrity for complex SoCs, with over seven years of experience. I have worked on different IPs on cutting-edge N4, N3, and N2 nodes, ensuring the electrical reliability of next-generation hardware.

Vaibhav has an experience of 13 years in Semiconductor industry, majorly focused at system-on-chip (SoC) level full-chip/subsytem level EMIR closure. Vaibhav holds a bachelors degree from JSS noida and is an alumnus of IIM Bangalore.

Abhishek is a seasoned professional with over 13 years of experience across Physical Design (PD), Electronic Design Automation (EDA), and Computer-Aided Design (CAD). He currently leads the PDCAD team at Google, where he leverages his deep industry knowledge to drive and own essential implementation and in-design signoff flows.

Sabya Sachi is part of Samsung (SSIR) CDS group. He has 7+ years of experience in the STA domain and contributed to multiple BIG DIE SOC tapeouts.

In 2 and Half decades of Design Experience, Sridhar has contributed to many ASICs spanning across Automotive, MCUs, Server SOCs, Mobile SoCs, Consumer electronics etc. areas in multiple design roles. He has specialized in PPA Optimization, Custom Clocking, Timing closure and SoC Execution flows. Currently Leading Samsung SoC Physical Design Execution Methodologies on latest process nodes for best-in-class PPA and signoff.

Ankit is currently working as GPU Timing Lead @ Qualcomm, Bangalore. He has around 14 years of industrial experience in Synthesis, Constraints Development, Timing Signoff of mult-million gate SOC's targeted for automotive applications, laptops, desktops and mobile SOCs. He has done his post graduation in ECE from Delhi College of Engineering.

Currently a Digital Design Engineer in Texas Instruments India, I am a VLSI enthusiast interested in optimizing the ASIC design flow. I am a part of TI for the past 3 years and my primary areas of work are Synthesis and STA. I have completed my M.Tech from IIT Bombay in Integrated Circuits and Systems. I am a person who is keen to put extra efforts in their work and push the learning curve higher, along with adding some versatility quotient in my knowledge.

Priyanka Sharma is a highly skilled PDK engineer with over five years of experience specializing in custom layout and CAD. Her career is marked by a strong dedication to precision and innovation and sincere approach towards her work, driven by a self-motivated spirit. She earned her M.Tech degree from NIT Jaipur and B.Tech degree from NIT Uttarakhand.

Currently working as PDK Engineer @Intel with 2 years of experience. I have done my M.Tech in VLSI from Defence Institute of Advanced Technology Pune and B.Tech in ECE from Indian Institute of Information Technology Trichy.

Engineering Manager with 13+ years of experience in semiconductor process design kits (PDKs), CAD and EDA tool integration, Application Engineer and team leadership. Proven expertise in developing and validating PDKs for advanced nodes, managing cross-functional teams, and delivering high-quality solutions for IC design.

Priya has a decade of experience in physical designing and verification of full custom analog/mixed-signal automotive-grade IPs like data converters & power management. In addition to layouts of complex analog circuits, Priya also has expertise in leveraging CAD methodologies to drive area-efficient digital design implementations. Her work has been recognized as publications in international conferences and ST-internal forums.

Priyanka priyanka.madaan@nxp.com , I have 9+ years of experience in layout designing.

Working as Lead Application Engineer for Custom layout design

Working as a Senior design Engineer in STMicroelectronics. Passionate VLSI engineer with over 8 years of experience in industry-leading projects and technologies. Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Design Rule Checking (DRC), Layout verses Schematic (LVS), EM & IR and Antenna check. Application-Specific Integrated Circuits (ASIC), Very-Large-Scale Integration (VLSI), Physical Verification, and Integrated Circuits (IC), Analog layout.

Arup Ray received the Ph. D. degree from the Advanced Development Technology Centre, Indian Institute of Technology Kharagpur in 2022. His Ph. D. dissertation was titled “Co-design of CMOS RF integrated circuits and on-chip antennas”, which focused on the design and challenges of integrating on-chip antennas and RF front end circuits like LNAs and rectifiers. He started his industry career with Qualcomm India Private Limited, Bangalore in 2022 as a Senior Engineer where he is currently working as Senior Lead Engineer. In Qualcomm, he has contributed to different capacities at large to the RFIC team for wireless mobile and connectivity circuits. He is a corporate member of the IEEE and the IE. He has served as the Secretary, and the Chair of the IEEE AP-MTTS Student Branch Chapter at IIT Kharagpur in 2017 and 2018 respectively. Apart from in-house Qualcomm conferences, he has also volunteered and participated in different IEEE conferences in India and abroad. He has contributed as an author or co-author to nine journal papers and three conference papers. He has served as a reviewer for the IEEE Antennas and Wireless Propagation Letters, Springer Scientific Reports, IETE Journal of Research, and the IET Microwaves, Antennas, & Propagation.

Working as Lead Application Engineer for Custom layout design

I am Analog layout Engineer at NXP Semiconductors with experience in full-custom Layout Design for mixed signal and analog IPs. I am specialized in deep submicron technologies, focusing on layout optimization, matching and parasitic design. I actively collaborate with circuit design teams to deliver high-performance, silicon- proven IP's.

Danish is working with Western Digital Bangalore India as a Technologist, leading an overall effort for Analog and Mixed Signal Design Verification and CAD development. His area of interests includes Custom IC Analog and Mixed Signal Design and Layout Automation, EDA methodology development, and Machine Learning and AI techniques for EDA. In past he had worked with Cadence, NXP and Maxlinear as an EDA Developer for custom IC tools and Methodology. Danish have received his B.Tech degree in Electronics and Communication from Jamia Millia Islamia, New Delhi and Masters in Microelectronics from Bits Pilani.

Sana is a Senior Engineer with almost 4 years of experience in the Custom CAD Team, ASIC BU at SanDisk, India. She holds a Masters degree in VLSI Design Engineering from Punjab Engineering College, Chandigarh. She is responsible for coming up with innovative methodologies, and developing automated flows for the MSIP CAD environment, evaluating EDA tools, and supporting Physical Verification & EMIR flows for MSIP teams.

Srinivasu Has 21 + Years of experience in Custom Layout, He joined Intel in 2106, currently he is working as Tech Lead in Intel India Technology pvt ltd. He has Experience in Analog IPs Like BGR, PLL, ADC, DAC, POR, GPIO, Mixed signal IPs like PCIE, TYPEC, e-PHY, and worked on SRAM and TCAM cells

I am Spoorthi S, currently working as Associate Staff Engineer at Samsung Semiconductors. I hold Bachelor's degree in Electronics and Communication and have 6 years of experience in layout design. My work spans a wide range of analog and mixed signal blocks, including data converters, PLLs, Bandgap references, SERDES and DDR interfaces across different technology nodes and foundries. I began my career as an intern at Cadence Design Systems, followed by Design Engineer I role at the same company, later transitioned to SSIR. I am passionate about solving complex design challenges in analog layout with the help of various EDA tools and programming languages.

Krutarth has been working with Cadence for last 2.5 years. Enabling Virtuoso Advanced flows with multiple customers. He has expertise in custom layout design automation.

Laya is been working with Cadence from last 8 years. Mainly on the Vitruoso advanced flow enablement across different customers. Apart from EDA, her past experience includes Analog layout implementation and advanced node layout methodology development. She is currently working with Samsung on enabling multiple technologies across different IP groups.

I am Wasimahmed Bepari. I graduated in Electronics and Communication Engineering from KLE Technological University (Formerly BVB), Hubli. I started my Career as an Analog Layout Engineer with Texas Instruments India in Power products centric mature tech nodes. Currently, I am delegated as an Associate Staff Engineer (Analog Layout) in Samsung Semiconductor India Research (SSIR) for High Speed Designs in advanced tech nodes. I derive immense pleasure in problem solving and piloting for newer EDA tools.

Senior Lead Engineer at Qualcomm, part of the CDE QDA team. Has been with Qualcomm for a year now, adding to his overall 7 years of industry experience in the custom IC space. He holds a Master's degree in VLSI from IIT Roorkee.

Staff Layout Engineer at Qualcomm India (RFWAN team) with 10+ years of experience in analog/RF layout. Holds a B.E. in Electronics from Mumbai University.

Technical Director and Verification Competence Manager. Over 24 years of experience in field of Semiconductor design, verification and worked across multiple and diverse products

With 14years of experience in Analog and Mixed Signal Verification at NXP semiconductors , I specialize in developing verification strategies and mixed signal simulations using Industry standard EDA tools.

Sachin S is working as a Staff Engineer at STMicroelectronics. He has over 8 years of experience and specializes in SV-UVM based IP verification and SoC AMS verification, including power management, data converters, and clocking. Sachin holds a Master of Engineering degree from MSIS Manipal.

Nishant Kaundal has nearly 12 years of experience in Mixed Signal verification domain & has a good know-how of SoC architectures, ranging from Mixed-Signal IPs to complex SoC integration. He has multiple paper-publications to his name, won various awards for his technical contribution & piloted various methodologies during his professional career. He is currently working as SoC_AMS Verification Engineer in GPAM division, based out of Greater-Noida, India.

Dr G S Javed is an Analog IC designer with 15+ years of experience in design of Analog and Mixed Signal (AMS) and SerDes IP Circuits. Since 2023, he has been the Analog IP Design Manager in the Advanced Design & Foundational IP (ADFIP) division at Intel Foundry. He received his M.S. and Ph.D. from the Indian Institute of Science (IISc), Bangalore. He worked on low power integrated instrumentation circuits for femtofarad capacitance sensing applications. In 2015, he founded King Consultants Education (http://tiny.cc/KingConsultants) to work on Design Thinking and Experiential Learning. He also is an advisor/guide for PhD aspirants. From 2020 - 2023, he was the Technical Lead - Analog for the High Bandwidth Memory (HBM) and DDR PHY team in Intel. From 2016 - 2020, he led the team on High-Speed Circuits delivering PCIE Gen4 PHY, USB3 PHY and MIPI MPHY, setup and managed the R&D team and managed a team of 10+ designers at Terminus Circuits Pvt Ltd. From 2012 - 2016, he was a Senior Research Fellow at IISc working on integrated sensor interfaces. He has over 30 peer reviewed journals and IEEE conference publications to his credit. He is an active IEEE volunteer of 15 years. He is a Senior Member of the IEEE (2016) and was inducted into the IEEE Eta Kappa Nu (HKN) - the Honour society of IEEE in 2017 for Academic Excellence. He has served as the Chairperson of IEEE TEMS Bangalore Chapter in 2023. He is associated as a Member of the EXECOM of IEEE CASS, SSCS, Sensors Council, SIGHT, Consultant Network and RFID council in Bangalore. He was the Educational activities Chair/Co-Chair in the IEEE Bangalore Section execom from 2017 - 2019. Currently, he is the Chairperson of IEEE Consultant Network Affinity Group (CNAG) Bangalore Chapter 2025. He is also an active speaker and motivator on Analog Circuit Design, High Speed Interface Design, Wireline Transceivers, Design Thinking, Entrepreneurship, Research Methodologies. Technical Writing and Spirit of Entrepreneurship. He has delivered over 200 invited talks in the last decade. He had also delivered multiple talks and workshops in University sponsored and ATAL Sponsored Faculty Development Programs (FDP).

An experienced problem solver for almost a quindecinnial, Shubham has diligently built his diverse career in field of Backend Layout Design, Automation, EM/IR Methodology and CAD domains. He currently leads the Design Methodology team at Intel which have frequently proven their excellence at automating & designing adroit methodologies for tools and flows to decrease costs and improve Org efficiency. He exhibits a solid track record of incubating teams from scratch and transforming them into high-performance groups to execute projects like clockwork. Post graduating in 2011, in Electronics & Communication and his Apprenticeship in VLSI from IIT Kharagpur, Mr. Shubham gained crucial experience on several design technologies at major design houses like LSI (Broadcom), ARM and Synopsys and gave it back to the academia by delivering guest lectures at IIT Delhi. Besides being a sports enthusiast, he is also the frontrunner in participating in top CSR initiatives of the firm.

Sukanta Saha is an EDA Tools Hardware Engineer with 3+ years of experience in the Design Methodology Engineering team at Intel's Technology Design Group. With extensive experience across leading-edge semiconductor process nodes, including Intel 20A, 7nm, 14nm, 16nm, and 22nm technologies, Sukanta plays a pivotal role in developing and enabling state-of-the-art Tools, Flows, and Methodologies that support Intel’s advanced design projects. In his current role, Sukanta actively contributes flow validation, and the creation of innovative methodologies aimed at optimizing design closure processes. As a core member of the Design Automation (DA) team, he is responsible for issue resolution, productivity enhancements, and maintaining key utilities to streamline EDA workflows. Sukanta has extensive experience with Cadence Virtuoso, and flow automation. His work focuses on bridging design methodology challenges with scalable automation solutions, ensuring first-pass success on Intel’s next-generation semiconductor designs.

Anshaj Shrivastava (IEEE S’18–M’24) received the B.E. degree in electronics and telecommunication engineering in 2013 from Bhilai Institute of Technology, Durg, India, in 2017, and the M.Tech(Res) and Ph.D. degrees in electrical communication engineering from the Indian Institute of Science, Bengaluru, India, in 2025. In July 2024, he joined Intel Technology India, Bengaluru, as an Analog Circuit Design Engineer. His current research interests include frequency synthesisers and mixed-signal circuits. Dr. Shrivastava has been a recipient of the IEEE Richard E. Merwin Scholarship (Fall 2023) and the Intel India Research Fellowship (2022-23) during his PhD, for the work titled "Towards a generalized approach in Design-for-Testability for Analog and Mixed-Signal ICs"

Completed M.Tech in IITD and 15+ Exp in Intel

I am currently working as a Design Engineer at NXP Semiconductors, where I have been contributing for the past one year in domain of PDK. I have recently completed my MTech in VLSI Design from Punjab Engineering College in 2025 after earning my BTech degree in Electronics and Communication Engineering from Chandigarh College of Engineering and Technology in 2023.

Vaibhav is a Staff Engineer/Member Technical Staff at STMicroelectronics and has more than 8 years of work experience. His area of interests include analog design, data converters and mixed-signal design.

Profile of PAVAN VERNEKAR : Pavan Vernekar with more than 10 years of experience in VLSI industry, works for Infineon Technologies as Senior Staff Engineer and into AMS verification domain. After pursuing Masters in VLSI from Manipal Institute of Technology - Manipal, started career as AMS Verification and Analog Integration Engineer for SoC’s in Microchip Technology, Currently Working for Infineon Technology in serving for deliveries of AMS verification for SoC’s for segments like Automotive MCs, power & sensor systems.

Sunny Kumar Sharma is a Principal Engineer at Micron Technology, located in Bangalore. With 10 years of experience Sunny specializes in Analog Circuit Design for High-Speed IPs like DDR, SERDES and ONFI. He has worked on circuits like High Speed IOs, DLL, Bandgap, Serializer etc.

Narendra manchineellais a Staff Asic layout Engineer at Micron Technology, located in Bangalore. With over 10 years of experience, narendra specializes in Analog and Mixed Signal layout development of analog components for high-speed AMS-IPs. Before joining Micron, Narendra worked at Acacia Communications Technologies.

Ravi Shekhda is a Staff AMS Verification Engineer at Micron Technology, located in Bangalore. With over 8 years of experience, Ravi specializes in Analog and Mixed Signal Verification, the development of behavioral models for analog components, and the digital verification of high-speed AMS-IPs. Additionally, Ravi contributes to system modeling development for high-speed AMS-IPs using Python/MATLAB. Before joining Micron, Ravi worked at Infineon Technologies and earned a master's degree in Embedded Systems from BITS-Pilani, Rajasthan.

Ronak Pandya is Lead Physical Desing Engineer at Micron Technology, located in Bangalore. With 9 years of experience, Ronak specialize in Physical Desing of high-speed memory interface IP and controller. Before joining Micron, Ronak worked at Samsung Semiconductor, Invecas and earned a master's degree in VLSI Desing from Thapar University Patiala, Panjab.

With 10 years at Intel, I have been an integral part of the CAD team, contributing to advancements in Extraction, Timing, Electrostatic Discharge (ESD) Solutions. My efforts have focused on enhancing semiconductor reliability and performance. I specialize in optimizing design processes and collaborating with cross-functional teams to drive innovation. I am dedicated to tackling complex challenges and delivering impactful results in the tech industry

Asociate Technical Director

Senior Staff DV Engineer at HPC group of Renesas Electronics India Private Limited

I have 6 years of DV experience and am passionate about the latest methodologies in DV

Subham has been working as DV Engineer in Texas Instruments . He joined TI as NCG in 2022 and has 3 years of experience in SoC DV and Functional Safety. He is a TUV SUD certified Functional Safety Engineer and has been involved with certification of multiple real-time MCUs for ASIL/SIL levels as per ISO26262 and IEC61508 standards . Outside of work he enjoys reading books and playing badminton

Associate Staff engineer

Sushree Bandita Panda, Staff Engineer

I hold a Master's degree from RV college of Engineering and have over 6 years of experience in the field of Digital Verification. I have worked extensively on the PMU(Physical Media Attachment) block, which is used in SERDES protocols and have contributed to the verification of 3D SOC's PMU(Power Management Unit) block. In addition, I have worked on multi-chiplet SOC based on ARM Cortex-M7 processors, gaining hands-on-experience in complex, high -performance design and their verification.

Siri Rajanedi is a Senior Design Verification Engineer at Analog Devices Inc. (ADI), where she has been part of the Engineering Enablement (EE) team since June 2022, following a one-year internship in the same group. Her work focuses on Functional Safety (FuSa) Design for Inspection (DFI), with a specialization in formal fault injection methodologies. Siri also contributes to the broader formal verification landscape.

Manikanta Having fulltime Mtech degree in VLSI from Manipal Institute Of Technology Manipal Karnataka . having 11+ years of experience in Functional Verification (IP/Subsystem/SOC) .worked on Various Protocols like ETHERNET USB UFS SDCARD EMMC POWER,AUDIO . currently working with SSIR from past 7+ years . and Managing and leading BOOTROM verification .

Sarang has been part of Sitara MPU SoC DV team since July 2023 . He has been working on Low Power Modes verification , Power Aware RTL DV , CPUSS IP DV and also has been part of DFT Design Verification . He is also interested in SoC Power Management Architecture and Functional Safety Automation .

Working in the Embedded Processors department at Texas Instruments. Graduated from College of Engineering Trivandrum (2021-2025 batch) in Electronics and Communication Engineering.

Ayushi Bapna is a SoC Design Verification Engineer at Texas Instruments with 6 years of experience working on wide range of ASICs (industrial, automotive). She has Masters degree in Microelectronics from BITS-Pilani with a keen interest in digital electronics, verification and current trends and innovation in semiconductor industry.

Amey Telang has consolidated experience of 15+ years in Front End over SoC/ASIC/FPGA Design and E2E deliverables. Serving at Samsung Semiconductor, heads peripheral design team for SoCs. The technical exposure focuses on Networking & Aero Space Domains with major involvements in SoC and IP design.

With experience on 25+ years of experience in design verification. At present working as director in Samsung heading part of SoC DV. Experience diversified in various product line in consumer, automotive and sensor lsi. In past worked in canon idc, Tata elxsi and synaptics.

I am Meghvendra Sinh Rathod , an ASIC Engineer specializing in Design Verification. I work with the Silicon Products team at Meta's Bangalore office. My expertise lies in ensuring the reliability and performance of silicon products through rigorous verification processes.

Shravani Kode is an ASIC Engineer in the Design Verification (DV) team at Meta. She holds a B.Tech in Electrical Engineering from IIT Bombay.

Working as IP verification engineer in MDRF-GPAM Noida team.

Gopika is a Senior Engineer at ADI, leading the Xcelium Methodology team within the EE-SVV group. With over 8 years of experience in Design Verification, she focuses on enhancing simulation performance and developing advanced debug solutions using the Verisium platform.

Madhav is currently involved in verification of complex mobile SoCs leading the signoff front-end DV methodologies involving SDC constraints, GLS verification/debug along with ownership of few key sub-systems that are compute intensive and peripherals. Madhav has an overall experience of 18+ years in Front end RTL & DV roles along with Physical design implementation working knowledge in his past stints at various semiconductor companies (Texas Instruments, PMC Sierra & AMD)

Vivek is a seasoned VLSI engineer with over 19 years of experience specializing in front-end functional verification. He holds a bachelor's degree in Electronics & Communication Engineering & has spent last 14+ years with Qualcomm as a verification engineer in Graphics Hardware team. He has played a pivotal role in verification sign off at various levels like sub-block/block/cluster/core levels of the cutting-edge Qualcomm Graphics cores over last decade plus which encompasses 7 generations of graphics cores.

I am Siva Gayathri, a Staff Engineer at MediaTek with 7 years of experience in Design Verification. Currently working on PCIe IP and SoC verification for ASIC projects.

Jaswanth Reddy is a Design Verification Engineer in Texas Instruments' EDA team since 2021. He holds a B.Tech in ECE from NIT Trichy and an M.Tech in ESE from IISc Bangalore. Jaswanth has pioneered DV regression flows and safety verification methodologies, successfully deploying solutions across multiple teams. He leads TI’s evaluation and integration of VerisiumApps and drives AI-assisted automotive solutions to enhance verification efficiency

Sanjana Jain is a Formal Verification Engineer in the GPU team at Qualcomm India. With two years of experience, she has successfully completed multiple formal verification projects, contributing to the development and deployment of formal verification methodologies in Qualcomm. Prior to her full-time role, Sanjana interned with the Intel Formal team, where she gained early hands-on experience with formal verification techniques. She has also authored papers and posters on formal methodologies at SNUG and internal Qualcomm conferences. Sanjana holds an M.Tech in System-on-Chip Design from IIT Palakkad.

Senior Engineer

Associate Staff Engineer

Senior Staff Engineer

Gaurav Malik is an Engineering Manager at Nvidia. He leads the verification and delivery of Nvidia’s Memory Subsystem Cluster, ensuring its accuracy and having bug free collateral. With extensive expertise in verifying multi-million-gate ASICs, Gaurav has worked across a variety of domains, including ARM Core, PCI Express, Ethernet-based designs, and ARM’s System Memory Management Unit in the past.

Silicon Design Verification Engineer with three years of experience in LPDDR controller implementation

I am a seasoned engineering professional with over 13 years of experience in the semiconductor industry. I began my career in 2012 and have steadily advanced through roles of increasing responsibility. Currently, I serve as a Senior Staff Engineer at Samsung Semiconductor India Research, where I specialize in Performance Verification Platforms for complex SoC designs. My work focuses on benchmarking and performance validation of GPUs and NPUs for mobile and automotive applications. I bring deep expertise in hybrid emulation platforms, system-level verification, and performance tuning, contributing to the development of next-generation semiconductor solutions.

I am working on pre silicon Performance Verification from last 5 years. I have experience on SoC PV and Embedded Software Development.

Saurav Chatterjee is the SoC Verification Lead for GPM products at STMicroelectronics, Greater Noida, with nearly 19 years of experience in MCU and MPU verification across Consumer, Industrial, and Automotive sectors. Previously at NXP, he focused on automotive SoCs emphasizing safety and security. His expertise includes ARM Cortex cores, interconnects, and memory subsystems, and he is passionate about the latest trends in semiconductor design and verification. Saurav holds a Bachelor’s degree in Electronics and Communication from Bangalore University. Outside work, he enjoys traveling, meeting new people, and following international sports where India competes.

SoC Verification Engineer with 10 years of experience in the field of SoC Verification and Emulation. Having worked previously with companies Qualcomm, NXPSemiconductors, Synopsys and HCL Technologies. Currently employed at STMicroelectronics, I have honed my skills in various aspects of SoC development and Verification, Emulation Model Build and Bring-up. Proficient with emulation platforms such as Palladium, Veloce, and ZEBU. Skilled in using JTAG-based debuggers and Lauterbach T-32 for efficient Presilicon Use case Verification. Extensive experience working with ARM Cortex and PowerPC architectures.

Experienced Emulation Engineer with 11+ years of experience across platforms like Palladium Z1/Z2/Z3 & Zebu ZS4 7 ZS5.

Bhanu leads the flagship Sub-System verification and validation aspects of Image signal Processing at SSIR. He has 5 years of experience working on conventional Design verification as well as emulation platform for camera.

Pranali Gaydhane completed her M.Tech in Instrumentation Technology from the Indian Institute of Science (IISc), Bangalore, and holds a B.Tech in Instrumentation and Control Engineering from College of Engineering Pune (COEP). She is currently working as a Digital Design Engineer at Texas Instruments, with over three years of experience in digital design, verification, and validation. Her areas of interest include digital system design, digital signal processing, and control systems.

Silicon (Design Verification) DV Engineer worked on - CPU cores - NoC verification at IP and SubSystem level - Interrupt Controller verification at SubSystem level

Design Verification Engineer at Google with 10 years of Industry experience across IP, SSWRP and SoC verification platforms

Ravi brings over 11 years of Design Verification experience in both IP and SoC environments. He currently leads SoC verification for Google's TPU, driving hardware acceleration for AI applications and research. Ravi holds a B.Tech in Electrical Engineering from IIT Roorkee.

B.Tech in E&C engineering from GB Pant University, Pantnagar, Uttarakhand INDIA. Having a 20+ yrs. experience of working in various domain IPs, SOCs Design verification and methodology development.

My name is Sudhakar Bansal, and I am currently working as a Director at SSIR(Samsung Semiconductor India Research), Banglore. I am passionate about functional verification, in-circuit emulation and task automation. With extensive experience in pre-silicon functional verification of about 18 years, I have worked for IP, Sub-system and SoC verification. I have a post-graduation degree from IIT-Roorkee with specialization in microelectronics.

Alok brings over 9 years of extensive experience in FPGA RTL design & verification, with a strong focus on SoC design porting to both custom and commercial prototyping and emulation platforms. Alok has contributed to virtual emulation platform development using QEMU on Palladium and ZeBu. His work integrates RTL into emulation tools through co-simulation methods, leveraging SystemC models. Outside of his professional expertise, Alok is passionate about optimizing prototyping and emulation methodologies. He enjoys exploring open-source software compilers, hardware compilers, and seeking innovative solutions for hybrid validation.

Aditya Chitrode is a distinguished Emulation Infrastructure Engineer with 12 years of industry experience. He specializes in the end-to-end bring-up of emulation models, from individual IPs to complex SoCs, and excels in developing the necessary infrastructure and transactors to support them. A key highlight of his career is pioneering the first-in-industry use of UVM-SystemC for driving traffic directly to the DUT in an emulation environment. This innovative methodology was instrumental in uncovering approximately 100 RTL bugs that had not been found in simulation.

Sharon Ruth is a Staff Engineer at Samsung Semiconductor India Research with 7 years of experience in Design-for-test DFT methodologies. She specializes in ATPG pattern generation, post silicon debug, ensuring high test coverage and yield for complex semiconductor designs.

Vivek Gopalkrishna is a Senior verification engineer in the Engineering Enablement team at Analog Devices. He is responsible for exploring and deploying Emulation and Portable stimulus methodologies to projects across ADI. He joined Analog Devices in 2022 prior to which he worked for 2 years on similar domains of verification. He holds a B.E. degree in Electronics and Communication Engineering from BMS College of Engineering, Bangalore.

Sheetal Jain working with Ola Krutrim SI Design India as Package Architect and Leading advance IC-packaging development for AI servers. Having 25+ years of careen spanning experience at Intel, ST-Ericsson, Infineon and Cadence and ISRO across multiple domains of Packaging, Silicon Design, Analog MS Tools and Flows, while starting career in PCB System design in ISRO. Sheetal has experience of working in different packaging technologies, advance 2.5D such as EMIBs or CoWoS for servers and very compact chip scale package or 3D package in Mobile/Modem world. Sheetal's knowledge on multiple domain make him a excellent Co-Design expert, helping optimizing package for across the domains and taking early accurate decision on package architecture. Sheetal hold a M Tech degree from IIT Delhi and committed to spread IC-Packaging related knowledge to evolving India Eco-system on assembly side whatever way possible.

Engineer with 9+ years of experience in Signal and Power Integrity, specializing in high-speed board and NAND package design, system-level simulation, modeling, and lab validation. Eager to contribute to SI/PI teams working on cutting-edge technologies, designing robust and cost-effective boards and packages through strong collaboration and innovation.

B.Tech from Anna university with 9+ years of experience in Signal and Power Integrity, NAND IC packaging, System-level simulation, High-speed board simulation, Serdes, IBIS, IBIS-AMI, Mixed-Signal HW/PCB design. Focused on addressing SIPI challenges to deliver innovative, high-impact engineering solutions.

Senior Manager at SanDisk with an M.Tech from IIT Delhi and 26 years of expertise in Signal and Power Integrity, high-speed link timing analysis, SI/PI modeling, and team leadership. Passionate about solving SIPI challenges and fostering innovation and business growth.

20 years of experience in high speed hardware design and simulation. Handling 50+ team members across various locations.

Dr. Santosh Bhagat is a Lead Application Engineer at Cadence Design Systems, where he leverages his strong background in radio frequency and microwave engineering. Holding a PhD from the Indian Institute of Technology, Delhi, and an MTech from the University of Delhi, he has also accumulated over 10 years of teaching and research experience. Throughout his career, he has developed a versatile skill set, enabling him to excel in electromagnetic (EM) and circuit simulations.

Gayetri, currently a Product Manage- RF, at Craftronics India Pvt Ltd, specializing in RF circuit Designs system design, RF PCB, and electromagnetic simulations. With over 4.2 years of industry experience and 8 years of teaching experience in wireless communication systems and telecommunications. Skilled in Antenna design Microwave Tees, Circuit Level design, and System Level design has proven comprehensive knowledge of understanding the fundamental concepts of wireless systems and technological expertise. Worked with multiple vendors to develop courses and training content. Gayetri, Master's degree Master’s Degree in Digital Communication Engineering from B.M.S College of Engineering Bangalore, Visvesvaraya Technological University and B.E, Electronics & Communications Engineering, from Guru Nanak Dev Engineering College, Bidar Visvesvaraya Technological University I am passionate about optimizing RF performance using Cadence tools and developing the case study for the different Customer that illustrate successful outcomes achieved with the tool, conduct live demonstrations with hands-on session that align with the customer’s specific goals, and building a compelling case for procurement with technical specifications for a winning approach.

Experienced PCB design engineer with 8 years of experience.

Senior Engineer, Signal Integrity (Micron). with 4 year experience in SI/PI domain. Obtained MTECH degree from IIT Kharagpur in RF and Microwave specialization. currently working on DDR5 memory high speed signal design. Senior Signal Integrity Engineer at Micron with nearly 4 years of experience in SI/PI. MTech in RF and Microwave Engineering from IIT Kharagpur and currently focusing on DDR5 high-speed signal design.

Senior Engineer

16+ years of experience in Package design and PCB Layout Designing, Schematic drafting, PCB 3D layout simulation, DFM, DFA & DFT for PCB. As a design engineer also good experience in multi-layer PCB, RF Design, very high-speed designs up to 60 GHz, high current power card designs, taking care of all Signal Integrity EMI & EMC Issues.

Thermal Engineer with 14+ years of experience in the Thermal design, Analysis and Validation. B.E in Mechanical Engineering. M.Tech in Thermal Power Engineering.

Hi, I am Senior Design Engineer at Qualcomm with total of 9Years experience.

Standard Cell Characterization Engineer

14 years of VLSI industry work experience primarily in RTL analysis, Synthesis, STA and PNR. Prior to it worked in IT infrastructure management and various EDA tools.

Prakhar Nayak is a experienced CAD and IPQA Engineer with 7+ years of experience in the semiconductor industry. He is currently a Senior CAD Engineer at Lattice Semiconductor, where he is responsible for Back End design methodology development and automation.

Experience 7.5 years. College : Mtech BMS engineering college Bangalore Working on Standard cell characterization projects. Char Flow enablement. QA scripting

I am a seasoned VLSI professional with close to 9 years of experience in the semiconductor industry, specializing in the full RTL to GDSII flow. Over the years, I've contributed to successfully closing multiple designs at advanced technology nodes, ensuring Performance, Power and Area targets are met with precision. My expertise spans across the complete physical design cycle, with a strong focus on timing closure, PPA optimization, and silicon accurate implementation. While I am not immersed in chip design, you will likely find me exploring the outdoors, planting trees, or playing outdoor games. I believe in balancing high-performance work with a grounded connection to nature and an active lifestyle.

Vedha S having over 8 years of industry experience is working as Staff Engineer at Samsung Semiconductor India Research. She specializes in standard cell design and characterization. She has worked on different tools like Liberate, Primelib, Virtuoso, Tempus, Voltus, Redhawk. She holds Master's in VLSI Design from VTU Belgaum.

Sukruthi is an Associate Staff Engineer at Samsung, originally from the City of Palaces, Mysuru. She has 7+ years of experience in Standard Cell Design and Characterization across advanced and legacy nodes. Her expertise includes timing, power, noise analysis, LVF, and library QA. She holds an Electronics Engineering degree from VTU.

Santhosh Kamatam, Digital Design Engineer, Logic Libraries team, NXP Semiconductors India Santhosh has ~7 years of experience. He has M.E in Microelectronics from BITS-Pilani. In his current role in NXP, Santhosh is working in the Standard Cell Library team developing customized circuits and different EDA views in various technology nodes. His technical contributions include 1 patent and 8+ conference publications in leading EDA forums. His areas of interest include Low Power circuit design and Physical design.

Abhishek is a seasoned professional with over 13 years of experience across Physical Design (PD), Electronic Design Automation (EDA), and Computer-Aided Design (CAD). He currently leads the PDCAD team at Google, where he leverages his deep industry knowledge to drive and own essential implementation and in-design signoff flows.

Silicon Engineer

Senior silicon cad engineer

Ganesh Andhavarapu is a Senior PD CAD Lead Engineer with over 18 years of experience specializing in RTL2GDS flows and methodology. Throughout his career, Ganesh has driven Physical Design CAD activities across leading semiconductor companies, contributing to the development and optimization of cutting-edge design automation solutions.

Passionate VLSI engineer with over 6 years of experience in physical design, RTL to GDSII implementation with focus on PPA tuning and workflows automation.

Physical Design Engineer in Texas Instruments with 5 year experience

Physical Design Engineer with 4+ years on experience in Power Grid Designs, IR Drop, PnR and Signoff.

Hariharan is a Digital design engineer at Texas Instruments with over 2 years of experience. He was worked across RTL, PD and AI.

Piyushkumar M. Chaniyara is DFT engineer with more than 9 years of experience in the field. He has been associated with Texas Instruments since March 2021 and have worked across multiple teams in Processors. His areas of interest are development of novel DFT architecture for scan and memory test. 

Satish Sajjanar is a DFT engineer with more than 8 years of experience in the field. Along with the DFT execution across various test aspects, he is also heavily involved in flow automation and key enabler for existing DFT flows developed for Processors devices. He has presented poster in TIITC’24 and tutorial at ITC India conference.

Sandip is an Application Engineer with Cadence Design Systems. His expertise includes High Power RF and Microwave Designs.

Currently working as Software Architect at Cadence Design Systems with 24+ years of experience. Extensive experience in Cadence' s PCB front-end tools for design capture and automatic schematic generation. Specialize in algorithms, data-structures and databases for EDA Tools and UI Design. Programming Experience: C/C++(generic programming, stl, boost) Perl, XML lex/flex, yacc/bison Specialties: Schematic Design Entry tools, Spreadsheet Based Design Entry Tools, Physical Design Automation, Program Planning and Tracking Customer Interfacing, Requirement Gathering and Functional Specification writing.

Application Engineer at Cadence Design Systems with 3 years of experience, specializing in PCB front-end design. Proficient in OrCAD, OrCAD X Capture for design and automated schematic generation, and in PSpice for circuit simulation and analysis. Actively involved in supporting design workflows, resolving complex tool-related challenges, and enabling efficient design and simulation practices. Passionate about empowering users through automation and best practices in front-end PCB design.

Galina Ross is a senior analog layout engineer at Samsung, with deep expertise in managing high-performing layout teams and driving innovation in advanced semiconductor design.

My name is Abraham George and I am a Senior Staff Layout Designer in SSIR Bengaluru. I I enjoy using my skills to contribute to the IO layout team activities in Samsung. I graduated from Kerala University with a bachelor's degree in Engineering and working with Samsung for past 7 years